|Subject:||Question about 802.3 clause 24 - Transimit/Transmit-Bits state diagram|
|Posted by:||SuperJoe (ming_…@yahoo.com)|
|Date:||Tue, 11 Sep 2007|
I have a very specific question about 802.3 clause 24 state diagram.
In Figure 24-7, Transmit Bits state diagram, looks like the state
transition happens every 8ns without interruption.
In Figure 24-8, Transmit state diagram, after "START STREAM K" state,
we need to start assigning ENCODE(TXD) data to tx_bits[4:0] in
"TRANSMIT DATA" state.
However, there is a extra latency for "ERROR CHECK" in between that
interrupts the "parallel-to-serial" function.
Could anyone explain to me because maybe I misunderstand the state
Thanks a lot.